Fabrication of Fine Via and Line / Space in Low CTE Film For Panel Fan-out Using a Dry Etching Technology

Smart ICT (Information and Communication Technology) such as “Big Data”, “Cloud computing” and Smart Functionalities such as Stand-alone Self-activating MEMS/Sensors construct Smart Systems which enable IoT (Internet of Things), IoE (Internet of Everything) thus Smart Society. High-density Packaging technologies such as 3D, 2.5D packaging scheme basing on TSV (through-Si via) technology and PWB (printed wiring board) packaging as high-density interposer are among key technologies to satisfy the requirements from the both smart semiconductor devices for AI (artificial intelligence), and smart functional devices for “Edge-computing”. Meanwhile MEMS/Sensors are required as multifunctionalities of stand-alone smart devices for wearable devices including smart phone, an important part of smart-systems. Thus, the demand of high density FO-SiP (fan-out system in packaging) is growing. In order to accomplish high-density packaging as homogeneous and heterogeneous integration, miniaturization of wiring in organic package is needful to MCM (multi chip module) system fabrication on the PWB. To obtain vias in a build-up film, the laser drilling process is widely used but there are three major restricting difficulties. The first is that it is difficult to make fine vias and line / space because of laser wave length limitation. The second is that wet desmear process to remove smear for each generation’s build-up films is also will be issue by swelling and silica-residue problem. And finally, such kind of technologies cannot intentionally control of surface roughness for build-up film. In this study, a fine via and line and space patterns processing below 10 μm with low surface-roughness in a low-CTE (coefficient of thermal expansion) Build-up film was achieved by using a plasma dry process. That technology applications are dry desmear and dry etching for fan-out wiring fabrication.