Finding the needle in the haystack: using full-chip process window analysis to qualify competing SRAF placement strategies for 65 nm
2006
It is widely understood that the IC Industry's adherence to Moore's Law is widening the gap
between the wavelength of light used in semiconductor manufacturing and the features that they
define. Increasingly, the patterning community has turned to higher complexity imaging solutions to
fill the gap. This steadily increasing complexity is placing a new burden on lithographers and
resolution enhancement technology engineers to guarantee that the highly complex patterning
strategies will work for all patterns. Traditionally, lithography strategies have been characterized
using relatively simple one-dimensional "litho test patterns." Real circuits are highly randomized
however, and complex two-dimensional interactions are the rule rather than the exception.
This paper extends the paradigm for use of newly available post-OPC verification (POV) technology
to the realm of RET development. We offer a case study where two competing 65-nm logic node
sub-resolution assist feature (SRAF) strategies for poly layer patterning are evaluated on a full chip
using commercially available post-OPC verification technology. We are able to evaluate differences
in CD control process window, SRAF printability (illustrated in Figure 1), MEEF sensitivity, and
catastrophic defect propensity. In several critical cases, we show silicon confirmation of the
simulated results. This methodology allows leveraging of existing full-chip POV technology to
enable the selection of the best SRAF strategy with minimal use of costly split lot silicon.
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