Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor

This paper describes the design and implementation of the vector scalar unit (VSU) in the first-generation CELL processor. VSU executes floating-point and vector media extension instructions. VSU contains 1.7 million transistors and occupies an area of 3.1 mm/sup 2/ in a 90nm PD-SOI technology. Extensive static and dynamic circuit techniques are used to optimize performance while minimizing area and power simultaneously. Full functionality is observed at 4.76 GHz, 1.3V supply and a chip temperature of 68/spl deg/C.