Old Web
English
Sign In
Acemap
>
authorDetail
>
Sherman M. Dance
Sherman M. Dance
University of Rochester
Computer science
Electronic engineering
Computer hardware
Electrical engineering
Double-precision floating-point format
4
Papers
35
Citations
0.00
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (4)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation
2011
ISSCC | International Solid-State Circuits Conference
Gary S. Ditlow
Robert K. Montoye
Salvatore N. Storino
Sherman M. Dance
Sebastian Ehrenreich
Bruce M. Fleischer
Thomas W. Fox
Kyle M. Holmes
Junichi Mihara
Yutaka Nakamura
Shohji Onishi
Robert Shearer
Dieter Wendel
Leland Chang
Show All
Source
Cite
Save
Citations (23)
The design and implementation of double-precision multiplier in a first-generation CELL processor
2005
ICICDT | International Conference on IC Design and Technology
Jente B. Kuang
T.C. Buchholtz
Sherman M. Dance
James D. Warnock
Salvatore N. Storino
Dieter Wendel
D.H. Bradley
Show All
Source
Cite
Save
Citations (2)
A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor
2005
ISSCC | International Solid-State Circuits Conference
Jente B. Kuang
T.C. Buchholtz
Sherman M. Dance
James D. Warnock
Salvatore N. Storino
Dieter Wendel
D.H. Bradley
Show All
Source
Cite
Save
Citations (10)
Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor
2005
CICC | Custom Integrated Circuits Conference
Tom Beacom
Timothy C. Buchholtz
Douglas Hooker Bradley
Jack Chris Randolph
Salvatore N. Storino
Mark Veldhuizen
Sherman M. Dance
Jente B. Kuang
Steve Schwinn
Susan M. Cox
Fred Ziegler
J. Kao
Chuck Li
Christophe Tretz
J. Cabellon
Andrew Patrick Freemyer
Matthew R. Tubbs
Show All
Source
Cite
Save
Citations (0)
1