A Scalable and Process Variation Aware NVM-FPGA Placement Algorithm

As non-volatile memory (NVM) based FPGAs gain increasing popularity, FPGA synthesis tools start to tune the synthesis flow to match NVM characteristics. State-of-the-art NVM FPGA placement algorithms tried to reduce the high reconfiguration cost induced by the costly NVM programming process. However, they are not only limited in scalability but also fail to consider process variation. This paper aims to overcome these limitations. Blocks in the NVM-FPGA are no longer uniform but classified into fast, slow, and dead blocks. Moreover, the proposed placement algorithm reduces computation complexity by not searching the entire design space for an optimal solution with minimum reconfiguration cost, but computing the reconfiguration cost just-in-time. Verilog-to-Routing (VTR)-based implementation confirms its effectiveness in reducing critical path length and speeding up the placement process, while still saving reconfiguration cost by up to 74.2%.