Stress voltage dependence HCI induced traps distribution in 60V LDNMOS

In this paper, lateral interface trap (N it ) distribution using variable top charge pumping (CP) technique is determined to present the mechanism of hot carrier degradation of 60V LDNMOS, processed in 0.42um technology. This is also correlated using TCAD simulation of hot carrier impact ionization. Traps distribution profile and simulated electric field shows the location of N it generation due to hot electron traps, and hot hole injection upon different HCI stress conditions. When HCI stress is done by gate voltages (V g =1.8 to 5.5V) and high drain voltage (Vd=60V), stress voltage dependent R on degradation is observed with negligible effect on V T and projected SOA (≫10yrs LT). For high gate voltage (V g =11V), trap generation is significant in the channel interface (N it ) and bulk oxide (N ot ), drift/N-well area resulting a enormous V T and R on degradation.