Circuit Reliability Analysis of In-Memory Inference in Binarized Neural Networks

Logic-in-memory (LIM) architectures based on the material implication logic (IMPLY) and resistive RAM (RRAM) devices enable the reconfigurable in-memory computation of logic operations, and can be exploited to deploy efficient realizations of Binarized Neural Networks (BNNs) on low-power devices at the edge of the network. However, an analysis of the reliability challenges affecting IMPLY-based BNN implementations is still missing. In this work, we highlight the reliability challenges of IMPLY-based realization of multilayer perceptron (MLP) BNNs. By using a physics-based RRAM compact model calibrated on three RRAM technologies from the literature we demonstrate that the smart IMPLY (SIMPLY) architecture solves the reliability issues affecting conventional IMPLY architectures and enables the in-memory computations of the operations needed for BNNs inference. The energy estimates for an inference task performed on a MLP BNN, show that even when considering the worst-case the SIMPLY implementation results in a $\gt 10^{2}$ energy-delay-product (EDP) improvement with respect to a conventional low-power embedded system.