Study of ELS technology for random logic LSI toward 32-nm node

There has been an ongoing request to make semiconductor devices smaller and smaller. The cellblock size of SRAM is predominated by both a gate-to-contact space and a poly-to-poly space. The gate-to-contact space is defined by the leakage value from the poly electrode. So we focused on the poly-to-poly space for all shrinkage. We have been studying connected line splitting techniques. We named it ELS (end of line splitting) technology. A critical issue is to control gaps between two narrow gate-poly's line-ends or between a narrow gatepoly's line-end and a neighboring wire-poly line due to lower contrast in low-k1 lithography. In the case of standard cells, especially, the patterning of narrow gate-poly projected to wire-poly is easy to shorten. To prevent this electrical short, designers avoid keeping a narrow gap and small chip size. In order to realize a narrower gap, a splitting technique, well-known and adopted in poly's line-ends of SRAM that are regularly arrayed, is effective. We are investigating how to extend this technique as ELS technology for random logic of poly toward creating a 32-nm node. In this paper, the authors focus on the following topics: 1) data preparation technique, and 2) experimental results. Then this technology for the poly layer of random logic LSI devices is compared with result of conventional single exposure and double pattering technology. In addition, the result that overlay control issue for ELS technology is not severe compared with pitch doubling technology is described. ELS technology can help the designer and our lithographer to reduce the gap and reduce the array grid size of standard cells.