Failure Mechanisms of Cascode GaN HEMTs Under Overvoltage and Surge Energy Events

Surge energy robustness of power devices is highly desired in many power applications such as automotive powertrains and power grids. While Si and SiC power MOSFETs withstand surge energy through avalanching, GaN high-electron-mobility transistors (HEMTs) have no avalanche capability. Recent studies have revealed that the p-gate GaN HEMT withstands surge energy through capacitive charging and fails when the peak capacitive voltage reaches its breakdown voltage (BV). This work, for the first time, studies the surge-energy robustness of a 650-V rated cascode GaN HEMT in the unclamped inductive clamping (UIS) test. The cascode GaN HEMT was found to withstand the surge energy via capacitive charging but accompanied by the Si MOSFET avalanching. Two failure modes were observed, both occurring in the GaN HEMT. The first mode is featured by a short between the HEMT gate and drain (cascode source and drain), while the second mode is featured by a short between the HEMT source and drain. Statistical results of multiple devices tested under different load inductance show that the second failure mode predominates. Additionally, the device failure voltage in mode I is statistically higher than that in mode II. Failure analysis of both modes is presented, and the physical explanations of the two modes and their competitions are proposed. These results provide important new insights into the robustness of cascode GaN HEMTs.