Design of CMOS buffers using the settling time of the ground bounce voltage as a key parameter

Design guidelines for CMOS buffers using the settling time of the ground bounce as a key parameter are given. Special emphasis is made on calculating the package inductance by an effective, lumped, power supply bus parasitic inductance. A trade-off between driver geometry, power supply bus geometry and settling time power supply is obtained. Finally, this paper uses a macromodel for modeling the ground bounce produced by the buffer in the switching state.