A comparative analysis of LFSR cascading for hardware efficiency and high fault coverage in BIST applications

Determination of the most appropriate test set is a critical task for high fault coverage in digital testing. Linear feedback shift registers (LFSR) is a common choice to generate pseudo-random patterns for any circuit under test. However, literature shows that pseudo-random generation is incapable of achieving high fault coverage in complex circuits under test. Moreover, a proportional amount of LFSR hardware is loaded with additional circuitry to implement weighted random and mixed-mode reseeding techniques. Despite dense research around weighted random and mixed-mode reseeding techniques, test pattern generation remains a high-cost block in built-in self-test architectures. This research paper uses the parallel concatenation of LFSRs to propose a simple, uniform, and scalable test pattern generator architecture for BIST applications. The proposed test pattern generator reduces the large use of memory elements in an LFSR. Moreover, the parallel concatenation of LFSRs enables the test pattern generator to supply divergent test sequences for comparatively high fault coverage. Fault simulations on combinational profiles of ISCAS’89 benchmark circuits show higher fault coverage with low hardware overhead as compared to standard LFSR.