A system for designing a semiconductor device, the reconstituted apparatus and method of using the system

This disclosure relates to a method for manufacturing a semiconductor device. The method includes comparing a diagram-design of a semiconductor device having a layout design of the semiconductor device. The method further includes generating layout style information, based on the layout design, and generating array edge information based on the layout design and circuit diagram design. The method further comprises selectively revising the layout design using intelligent auxiliary cell inserting means of the layout style information and the array edge information. The method further comprises performing a verification of a design rule for the revised layout design by the layout style information and the array edge information. This disclosure also relates to a system for manufacturing a semiconductor device and a semiconductor device.