A 100MHz ladder FeRAM design with capacitance-coupled-bitline (CCB) cell
2010
A new ladder FeRAM architecture with CCB cell and early plateline pull-down read scheme has been proposed. This enables 10-ns read/write cycle and 8-ns access using a 0.35µm 2 cell with 0.145µm 2 ferroelectric capacitor.
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