Impacts Single Patterning ILT for Advanced Memory Challenging Design

Memory design continues to scale to smaller area and higher density to meet the industry requirements for high-speed memory performance. The aggressive scaling leads to lithographic difficulties for patterning resolution, 2D CD control and process window. Double patterning technology (DPT) can be employed to overcome lithographic and traditional OPC limitations for low K1 values, but the cost can be high. Inverse Lithography Technology (ILT) has also been demonstrated as capable of extending the use of single patterning to lower K1 cases while achieving acceptable lithographic quality and cost for advance memory semiconductor designs. This paper will present results of single patterning ILT for challenging region of DRAM contact layer. ILT derived rule-based assist features are used for optimal process window. The ILT single patterning solution was developed with process window and sidelobe aware costs functions, which was needed to achieve the lithographic QOR for single patterning. For mask processing turn around time (TAT) and consistency, a pattern-based hierarchy extraction technique was used to generate cell repetition to achieve high compression processing of a full chip flat layout. Along with QOR and TAT data, wafer and simulation results will be shown for single-patterning ILT.