A 28Gbps high-speed SERDES transmitter

A high-speed (28Gbps) interface transmitter design based on a Source-Series Terminated drive structure is introduced. The architecture and principle of the entire TX are described in detail; the clock duty cycle calibration (DCC) circuit with digital-analog hybrid control is used to effectively reduce the DCD; and a transmitter unit based on SST structure impedance tuning and weighted balance decoupling is improved The structure greatly reduces the complexity of logic control. The transmitter circuit can be used for FPGAs that require a transmission rate of 1 Gbps~28 Gbps. The design is made with SMIC14 nm FinFET technology. The sample test results show that when the output rate is 28 Gbps, the transmitter's indicators meet the PCIE 4.0 protocol standard.