Innovative Design of Crackstop Wall for 14nm Technology Node and Beyond

2018 
Crackstops play an important role in protecting the IC prime from moisture ingress as well as impinging cracks. The introduction of thinner BEoL dielectric layers and ULK materials in advanced CMOS technology resulted in more vulnerable crackstop structures. Through Silicon Via (TSV) technology allows the creation of solid copper monolith walls that lack any seams or weak points associated with the conventional layer by layer construction of traditional die seals or crackstops. It was found in previous work [1] that the solid copper crackstop monolith was a superior structure with nearly two times the likelihood to stop the propagation of impinging cracks. However, laboratory experiments demonstrated that cracks were able to bypass the impenetrable solid copper wall through either the underlying silicon interface or unintended thin oxide interface on the upper section of the monolith wall. To address this issue a series of different crackstop architectures that use through silicon via technology have been proposed. These designs incorporate and leverage different architectural elements in an attempt to force the crack's propagation path into the solid copper wall. To assess the various proposed crackstop design's efficiency at stopping a crack, a series of FEM simulations were performed. Simulations were used to study the possibility of crack propagation in a BEoL/Far BEoL stack at the following interfaces: a) copper/copper or copper/aluminum interface; b) the dielectric surrounding the crackstop; and c) the copper/Si interface. Simulations showed in the case of an added bumper extension that cracks are three times less likely to propagate in the Far BEOL at the Al/Cu interface and two times less likely to propagate at the Cu/Si interface. Simulations also showed that the bumper extension with sacrificial dielectric is very efficient in trapping the cracks. Cracks were two times more probable to propagate away from the Cu/Si interface into the sacrificial dielectric and above it.
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