A GALS Infrastructure for a Massively Parallel

Neural Network Archi-tecture)projectattheUniversityofManchesteraimsatsimulating a billion spiking neurons in real time.Fortunately, such an application is an ideal candidatefor massive parallelism, and unlike some forms ofparallel processing, it needn’t maintain consistency inshared memories. Neural models running in such anenvironment communicate by means of spike events,which occur when a neuron is stimulated beyonda given threshold. The spike events must be commu-nicatedtoallconnectedneurons,withtypicalfan-outson the order of 1,000.Figure 1 illustrates the basic Spinnaker architecture.EverynodecomprisesaSpinnakerchipmultiprocessor(CMP) and a memory chip. Six bidirectional linksconnect the nodes. The Spinnaker chip, whichconstitutes the basis of the system, houses severalsynchronous ARM9 processor cores, chosen primarilyfor their high power efficiency. Each processor modelsup to around 1,000 individual neurons, and a packet-switched network carries spike events to other proces-sors on the same or other connected chips. At start-up,the processors perform a self-test; the first to completethe test successfully appoints itself the monitor pro-cessor and thereafter performs management tasks.Each processor corehas about 100 Kbytes oflocalmemoryonchip.Asa supplement, a singleexternal mobile double-data-rate SDRAM deviceof 128 Mbytes providesa large shared-memoryresource used primarilyforstoringneuralweights.Each chip’s six bidirectional links permit chipnetworks of various topologies. Interchip communica-tion uses self-timed channels, which, although costlyintermsofwires,aresignificantlymorepowerefficientthan synchronous links of similar bandwidth. Weexpect a flat 2D interconnect to suffice for theintended application, and this will allow straightfor-ward layout on PCBs. However, this does not implythat the system can model only 2D neural structures.Spinnaker can model networks in two, three, or moredimensions. Thekey to this flexibilityis that Spinnakermaps each neuron into a virtual address space.Assignments can be arbitrary, though assignmentsrelated to physical structure are likely to improvemodeling efficiency. Neurons can be allocated to anyprocessor, and the routing tables must be configuredto send the neural events accordingly. Further detailsof the neural simulations are available elsewhere.