Electrical properties of metal-oxide-semiconductor structures with low-energy Ge-implanted and annealed thin gate oxides

The electrical characteristics of low-energy (3keV) Ge-implanted and, subsequently, thermal annealed SiO2 layers are investigated through capacitance-voltage (C-V) and conductance-voltage (G-V) measurements of metal-oxide-semiconductor capacitors. Particular emphasis is placed on the properties of such gate oxides for memory applications. Capacitance measurements at flatband voltage before and after the application of constant voltage stress in the accumulation regime indicate that the charge trapping behavior of the devices undergoes a major change after annealing at temperatures higher than 910°C. The latter change is identified as a relocation of Ge atoms mainly toward the upper portion of the oxide with a significant fraction of them leaving the oxide; a finding in harmony with secondary ion mass spectroscopy analysis. The interface trap density (Dit) for the thin (9–12nm) implanted oxides decreases with increasing annealing temperature, approaching at 950°C the Dit levels in the mid-1010eV−1cm−2 rang...