RF Clock Distribution System for a Scalable Quantum Processor in 22-nm FDSOI Operating at 3.8 K Cryogenic Temperature

We present an RF clock distribution system for a fully integrated and scalable quantum processor core operating at 3.8 K. An external 2.4 GHz signal is guided from the generator to the flip-chip package IC through a cryogenic coaxial cable. The choice of coaxial cable and the clock routing design on the PCB and IC, minimizes path loss and coupling to the supplies, the I/O signals, and more importantly the sensitive quantum core. The clock integrity up to the quantum core is maintained and verified by the jitter measurement of 0.8 ps from a test port while all circuitry within the cryo-cooler operates within the thermal load specification of 1.5 W.