Novel Method Enabling Forward and Backward Propagations in NAND Flash Memory for On-Chip Learning

In this work, a novel synaptic array architecture enabling forward propagation (FP) and backward propagation (BP) in the NAND flash memory is proposed for the first time for on-chip learning. In the proposed synaptic architecture, positive synaptic weight and negative synaptic weight are separated in different arrays to enable weights to be transposed correctly. In addition, source-lines (SLs) are separated, which is different from the conventional NAND flash memory, to enable both the FP and BP in the NAND flash memory. By applying input and error input to bitlines (BLs) and string-select lines (SSLs) in NAND cell array, respectively, accurate vector–matrix multiplication is successfully carried out in both FP and BP eliminating the effect of pass cells. At a read voltage of 2 V, the inference accuracy of 95.58% which is comparable to that of 95.81% obtained with perfect linear device is achieved. The proposed on-chip learning system is much more robust to weight variation compared to the off-chip learning system. Finally, superiority of the proposed on-chip learning architecture is verified by circuit simulation of a neural network.