Back-channel effect on SOI CMOS for high voltage power ICs

Silicon On Insulator (SOI) technology is becoming very attractive for power ICs because CMOS controlled circuits and high voltage devices can be integrated on a single die. For applications such as inverters for electronic ballast, motor control and power source, the CMOSFETs and power devices are required to operate in high-side mode. Recently, it has been shown that power devices in SOI substrate with silicon thickness (t/sub SOI/) of around 1 /spl mu/m have excellent characteristics. The back-gate-bias effects on SOI Lateral DMOSFET (LDMOS) and ultra-thin SOI CMOS have also been reported. However, there has been no report studying the leakage characteristics of SOI CMOS with silicon thickness of around 1 /spl mu/m under a very large negative back gate bias typical of high-side operations. In this paper, we present such back-channel effect on SOI CMOS. The possible solutions are discussed with numerical simulation results.