Test Challenge for Deep Sub-micron Era - Test & Diagnosis Platform: STARCAD-Clouseau

The progress in miniaturization of semiconductor process technology has brought new issues to SoC test in 32nm technology and beyond. The increasing variation due to the semiconductor miniaturization causes the increase of parametric failures. As a result, the conventional test technology is suffering from the loss of test quality and the increase of test cost. In addition, there is increasing number of SoCs used in portable products running on battery and so new low-power design technologies are emerging. In order to cope with this evolution, new test technologies for such low-power design are required. Also, some test technologies considering power-supply noise is becoming important for the low-power SoCs, since the margin of power-supply noise is small. Furthermore, it becomes important to investigate the cause of failures. Especially for delay defects, it becomes difficult to identify the cause of failures by physical analysis such as a light emission microscopy. So it is important to reduce the number of fault candidates by a fault diagnosis tool. In STARC, we have been developing a test and diagnosis platform, STARCAD-Clouseau, to solve the above problems related to test and diagnosis. In this keynote, I will show some of our research activities for variation-aware test, power and noise aware test, and fault diagnosis.