SiN-capped HfSiON gate stacks with improved bias temperature instabilities for 65 nm-node low-standby-power transistors

This paper describes the SiN-capped HfSiON gate stacks for 65 nm-node low-standby-power transistors with improved bias temperature instabilities (BTI). By employing SiN-cap on HfSiON and the counter-implant for adjustment of pFET's threshold voltage (V/sub TH/), the symmetrical V/sub TH/ values for nFETs and pFETs have been obtained. The nitrogen incorporation in the interfacial oxide prevents the interface states generation under positive bias temperature stress. Negative BTI can be improved by reducing the thickness of SiN-cap. 10-year lifetimes for both positive and negative BTI have been achieved.