Offset Voltage Analysis and Enable Signal Rise Time Control Based Offset Reduction Technique of Current-Latched Sense Amplifier

This paper analyzes input referred offset voltage (V OS ) of a current-latched sense amplifier (CLSA) caused by a mismatch of input NMOS pair, latch NMOS pair, latch PMOS pair, and precharge PMOS pair. In addition, SA enable rise time control based V OS reduction technique is proposed. HSPICE simulation results based on industry-compatible 28-nm model parameters show that the proposed technique can reduce V OS caused by latch NMOS pair's mismatch by 33%.