Effectiveness of Embedded-SiGe in Super-Critically-Thick Strained-SOI

Biaxially-strained silicon directly on insulator substrates (SSOI) are a promising source of further strain engineering in future CMOS technology nodes [1]. SSOI layer thickness beyond critical thickness allow integration with current leading-edge SOI technologies [2]. However, any use of wafer-level biaxial strain techniques should not compromise the effectiveness of processinduced uniaxial stressors, such as compressive and tensile overlayers, embedded-SiGe, and stress memorization [3]. Of these process-induced uniaxial stressors, embedded-SiGe is of greatest interest since it accounts for the largest performance increase, and based on general understanding [4,5] should not be fully compatible with SSOI. SiGe is in compression when embedded in Si, due to the lattice mismatch between SiGe and Si, and from this, generates compressive stress in the channel region. If the Si itself is under tensile strain, as would be the case with SSOI, then any SiGe grown on it would be relaxed and should not generate compressive channel stress. The biaxially-strained SSOI wafers used in this experiment were manufactured by growing strained-Si on a 20% relaxed SiGe buffer layer, followed by a wafer bonding process to form SSOI. A modified production process with 4 uniaxial stressors [3] was run on the SSOI wafers. The embedded-SiGe is grown epitaxially at a concentration of 20% Ge, matching the original lattice “template” on which the SSOI layer was formed. A cross sectional TEM of the PMOS with embedded-SiGe on 48nm-thick SSOI is shown in Fig. 1. SSOI strain is characterized on patterned product wafers throughout the process using Raman spectroscopy, with resolution down to 1um. The SSOI remains strained through the STI process, through SiGe cavity etch, and through surface pretreatment just prior to epitaxial growth, as shown in Fig. 2. Both N-Active and P-Active SSOI regions remain strained, where the N-Active region does not receive an embedded-SiGe cavity etch, and is covered by a multilayer hardmask during surface pretreatments prior to SiGe epitaxy. The P-Active region receives cavity etch and surface pretreatments. Fig. 3 and Fig. 4 show that the ION versus IOFF characteristics in saturation and linear regimes, respectively. The drive current improvement from embedded-SiGe is equal if not more for SSOI than for the standard SOI control. NMOS drive currents are unaffected by the addition of the embedded-SiGe to PMOS. Thus, the uniaxial stress generated by the embedded-SiGe is fully effective on SSOI. Without lateral lattice mismatch between embedded-SiGe on SSOI, this result points to the importance of the vertical lattice mismatch in stress generation from embedded-SiGe. Normally it has been assumed that the lateral lattice mismatch was of greater importance due to [4]. Full compatibility of embeddedSiGe on SSOI demonstrates however, that vertical lattice mismatch is the dominant mechanism for channel stress generation from embedded-SiGe.