Advanced chip package interaction qualification for critical stacks in combination with Cu pillar interconnect technology

For mobile applications, advanced silicon technology nodes are using Back End Of Line (BEOL) stacks with Ultra Low-k (ULK) materials. Employing these ULK materials in combination with advanced Flip Chip (FC) packages requires a profound understanding of the chip package interaction (CPI). To match high I/O and reduced pitch requirements, Cu pillars are widely used as first level interconnect technology [MCC15, KAU15, KUE12 LEE013, RYA12]. In general, Cu pillars are known to increase the stress in the BEOL stacks compared to conventional SnAg interconnects. More viscoplastic deformation occurs in SnAg interconnects and reduces the stress in the BEOL. Therefore, the combination of Cu pillars and aggressive low cost, high performance BEOL stacks with ULK materials requires a systematic concept for the CPI qualification. This includes window studies and margin tests and requires a close collaboration of silicon foundry and the assembly facility.