Reduced-Order VSI Model for Stability Analysis and Low-Cost PHIL Realizations

One of the main critical design issues in current high-power systems is to carry out a field test in order to analyse power system stability due to its high complexity and cost. Hence, power-hardware-in-the-loop (PHIL) technology provides a powerful tool for testing scenarios where there is a high-power interchange providing preliminary analysis of the system stability. For that purpose, it is necessary to model the impedances of the different components used in the PHIL simulation. In DC-distributed applications, three-phase voltage-source inverters (VSI) are commonly used as load converters, and hence, its input impedance model is required in order to emulate its behaviour regarding stability analysis. Since a full-order approach requires a high-expensive real-time digital simulator to use PHIL technology, this paper proposes a reduced order input impedance model of a three-phase VSI which allows to overcome expensive PHIL implementations. First we show how the region of stability limits of both models are in good agreement, using a Lyapunov-based method. Then, we demonstrate the validity of a reduced-order model with respect the full-order approach, using frequency domain criteria and time-domain simulations. Finally, the validity of a reduced-order input impedance model of a three-phase VSI with respect the full-order approach has been evaluated to overcome the expensive PHIL implementations.