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F.M. Lassandro
F.M. Lassandro
Parallel computing
Computer science
Computer hardware
CPU cache
Instruction set
2
Papers
37
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A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect
1999
IEEE Journal of Solid-state Circuits
Carmine Nicoletta
Jose Alvarez
E. Barkin
Chai-Chin Chao
B. Johnson
F.M. Lassandro
P. Patel
D. Reid
Hector Sanchez
J. Seigel
Michael Snyder
S. Sullivan
S.A. Taylor
Minh Vo
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Citations (19)
450 MHz PowerPC/sup TM/ microprocessor with enhanced instruction set and copper interconnect
1999
ISSCC | International Solid-State Circuits Conference
Jose Alvarez
E. Barkin
Chai-Chin Chao
B. Johnson
M. D'Addeo
F.M. Lassandro
G. Nicoletta
P. Patel
Paul A. Reed
D. Reid
Hector Sanchez
Joshua Siegel
S. Sullivan
Scott D. Taylor
Minh Vo
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Citations (18)
1