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M. D'Addeo
M. D'Addeo
CPU cache
Computer hardware
Computer science
PowerPC
Out-of-order execution
2
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42
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450 MHz PowerPC/sup TM/ microprocessor with enhanced instruction set and copper interconnect
1999
ISSCC | International Solid-State Circuits Conference
Jose Alvarez
E. Barkin
Chai-Chin Chao
B. Johnson
M. D'Addeo
F.M. Lassandro
G. Nicoletta
P. Patel
Paul A. Reed
D. Reid
Hector Sanchez
Joshua Siegel
S. Sullivan
Scott D. Taylor
Minh Vo
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Citations (18)
A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller
1997
IEEE Journal of Solid-state Circuits
Gianfranco Gerosa
Mike Alexander
Jose Alvarez
C Croxton
M. D'Addeo
A.R. Kennedy
Carmine Nicoletta
J.P. Nissen
Ross Philip
Paul A. Reed
Hector Sanchez
S.A. Taylor
B. Burgess
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Citations (24)
1