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Michael Sesterhenn
Michael Sesterhenn
Physics
Optoelectronics
Transistor
Electronic engineering
Nanoelectronics
5
Papers
22
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Highly scalable sub-50nm vertical double gate trench DRAM cell
2004
IEDM | International Electron Devices Meeting
Till Schloesser
Dirk Manger
Rolf Weis
Stefan Slesazeck
F. Lau
Stefan Tegen
Michael Sesterhenn
M. Muemmler
Joachim Nuetzel
D. Temmler
B Kowalski
U. Scheler
M. Stavrev
Daniel Koehler
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Manufacturing method of a grave capacitor with an insulation collar, which is electrically connected through a buried contact on one side with a substrate, in particular for a semiconductor memory cell
2003
Thomas Hecht
Till Schloesser
Michael Sesterhenn
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Fully depleted surrounding gate transistor (SGT) for 70 nm DRAM and beyond
2002
IEDM | International Electron Devices Meeting
Bernd Goebel
Jörn Lützen
Dirk Manger
Peter Moll
K. Mümmler
Martin Popp
U. Scheler
Till Schlösser
Harald Seidl
Michael Sesterhenn
Stefan Slesazeck
Stefan Tegen
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Citations (18)
Verfahren zur Herstellung eines integrierten Halbleiterspeichers
2002
Daniel Köhler
Dirk Manger
Martin Popp
Till Schlösser
Michael Sesterhenn
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Integrated semiconductor memory and methods of manufacture
2002
Dirk Manger
Martin Popp
Till Schlösser
Michael Sesterhenn
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