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Rajeev Malik
Rajeev Malik
Electronic engineering
Dram
Engineering
Electrical engineering
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4
Papers
11
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High performance single work-function tungsten gate CMOS devices for gigabit DRAM
2001
IEDM | International Electron Devices Meeting
Woo-tag Kang
Oleg Gluschenkov
Boyong He
Yujun Li
Rajeev Malik
Lawrence A. Clevenger
Irene McStay
W. Robl
Rolf-Peter Vollertsen
G. Massé
G. La Rosa
Kilho Lee
C. Murthy
Christopher Parks
Rick L. Mohler
W.Bergner
E. Crabbd
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Citations (3)
Shallow n/sup +//p/sup +/ junction formation using plasma immersion ion implantation for CMOS technology
2001
VLSIT | Symposium on VLSI Technology
K. Y. Lee
Jai-Hoon Sim
Yujun Li
Woo-Tag Kang
Rajeev Malik
Rajesh Rengarajan
Susan Chaloux
James David Bernstein
Peter L. Kellerman
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Citations (4)
A 0.135 pm2 6F2 Trench-Sidewall Vertical Device Cell for 4Gb/l6Gb DRAM
2000
Carl J. Radens
U. Gruening
Jack A. Mandelman
Mihel Seitz
Thomas W. Dyer
D. Lea
D. Casarotto
Lawrence A. Clevenger
Larry Alan Nesbit
Rajeev Malik
Scott Halle
Stephan Kudelka
Helmut Tews
R. Divakaruni
Jai-Hoon Sim
Alvin W. Strong
D. Tibbel
N. Arnold
Scott J. Bukofsky
J. Preuninge
Gerhard Kunkel
Gary B. Bronner
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Citations (1)
A 0.135 /spl mu/m/sup 2/ 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM
2000
VLSIT | Symposium on VLSI Technology
Carl J. Radens
U. Gruening
Jack A. Mandelman
Mihel Seitz
D. Lea
D. Casarotto
Lawrence A. Clevenger
Larry Alan Nesbit
Rajeev Malik
Scott Halle
Stephan Kudelka
Helmut Tews
Ramachandra Divakaruni
Jai-Hoon Sim
Alvin W. Strong
D. Tibbel
N. Arnold
Scott J. Bukofsky
Juergen Preuninger
Gerhard Kunkel
Gary B. Bronner
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Citations (3)
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