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M. Hajra
M. Hajra
Intel
Electronic engineering
Electrical engineering
Architecture
Flash memory
Scaling
2
Papers
8
Citations
0
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A Self-Aligned Contact Architecture with W-Gate for NOR Flash Technology Scaling
2007
VLSI-TSA | International Symposium on VLSI Technology, Systems, and Applications
Alain Blosse
M. Wei
V. Bhachawat
M. Hineman
Randy J. Koval
J. Gorman
D. Kau
J. Tewg
L. Wang
M. Hajra
P. Schroeder
B.J. Woo
A. Fazio
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Citations (3)
Flash ETOX/spl trade/ virtual ground architecture: a future scaling direction
2005
VLSIT | Symposium on VLSI Technology
Randy J. Koval
V. Bhachawat
C. Chang
M. Hajra
David L. Kencke
Y. Kim
C. Kuo
T. Parent
M. Wei
B.J. Woo
A. Fazio
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Citations (5)
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