Old Web
English
Sign In
Acemap
>
authorDetail
>
Manabu Senoh
Manabu Senoh
Computer science
Dram
Electronic engineering
Embedded system
Macro
5
Papers
8
Citations
0.00
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (5)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
0.13-/spl mu/m 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability
2002
IEEE Journal of Solid-state Circuits
Hirohito Kikukawa
Shigeki Tomishima
Takaharu Tsuji
Toshiaki Kawasaki
S. Sakamoto
Masatoshi Ishikawa
Wataru Abe
Hiroaki Tanizaki
Hiroshi Kato
Toshitaka Uchikoba
T. Inokuchi
Manabu Senoh
Y. Fukushima
M. Nirro
Masanao Maruta
Akinori Shibayama
Tsukasa Ooishi
Kazunari Takahashi
Hideto Hidaka
Show All
Source
Cite
Save
Citations (0)
A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications
2001
IEEE Journal of Solid-state Circuits
Shigeki Tomishima
Takaharu Tsuji
Toshiaki Kawasaki
Masatoshi Ishikawa
T. Inokuchi
Hiroshi Kato
Hiroaki Tanizaki
Wataru Abe
Akinori Shibayama
Y. Fukushima
Mitsutaka Niiro
Masanao Maruta
T. Uchikoba
Manabu Senoh
S. Sakamoto
Tsukasa Ooishi
Hirohito Kikukawa
Hideto Hidaka
Kazunari Takahashi
Show All
Source
Cite
Save
Citations (4)
24.4 A 1.0V 230MHz Column-Access Embedded DRAM Macro for Portable MPEG Applications
2001
International Solid-State Circuits Conference
Shigeki Tomishima
Takaharu Tsuji
Toshiaki Kawasaki
T. Inokuchi
Hiroshi Kato
Hiroaki Tanizaki
Wataru Abe
Akinori Shibayama
Y. Fukushima
Mitsutaka Niiro
T. Uchikoba
Manabu Senoh
S. Sakamoto
Hirohito Kikukawa
Hideto Hidaka
K. Takahashi
Show All
Source
Cite
Save
Citations (0)
A 1.0 V 230 MHz column-access embedded DRAM macro for portable MPEG applications
2001
ISSCC | International Solid-State Circuits Conference
Shigeki Tomishima
T Tsuji
Toshiaki Kawasaki
Masatoshi Ishikawa
T. Inokuchi
Hiroshi Kato
Hiroaki Tanizaki
Wataru Abe
Akinori Shibayama
Y. Fukushima
Mitsutaka Niiro
Masanao Maruta
T. Uchikoba
Manabu Senoh
S. Sakamoto
Tsukasa Ooishi
Hirohito Kikukawa
Hideto Hidaka
K. Takahashi
Show All
Source
Cite
Save
Citations (4)
0.13um 32Mb/64Mb embedded DRAM core with high efficient redundancy and enhanced testability
2001
ESSCIRC | European Solid-State Circuits Conference
Hirohito Kikukawa
S. Tomishima
T Tsuji
Toshiaki Kawasaki
S. Sakamoto
Masatoshi Ishikawa
Wataru Abe
Hiroaki Tanizaki
Hiroshi Kato
T. Uchikoba
T. Inokuchi
Manabu Senoh
Y. Fukushima
Mitsutaka Niiro
Masanao Maruta
Akinori Shibayama
Tsukasa Ooishi
Kazunari Takahashi
Hideto Hidaka
Show All
Source
Cite
Save
Citations (0)
1