Effect of grain boundaries on electrical properties of polycrystalline graphene

Abstract Since it was discovered, synthesizing large area graphene sheets by chemical or epitaxial methods is the conventional method for the application of graphene's outstanding properties. Unfortunately, CVD grown graphene is polycrystalline in nature with grain boundaries (GBs) unlike exfoliated single crystal graphene flakes. These GBs are known as the main source of degrading mechanical, chemical and electrical properties of CVD graphene. Nematic liquid crystal was employed to visualize grains and boundaries and to calculate the atomic orientation of adjacent grains. Electrical performance of various GB devices was observed, and the role of grain boundaries on the ultimate electrical performance was investigated. The same work was carried out at low temperature (∼7 K) to minimize the perturbation of two-dimensional electron which originated from the graphene lattice vibration. Interestingly, it was observed that there was no significant effect of the grain boundaries on the overall electrical performance of devices even at low temperature. These results lead to the conclusion that the grain boundaries in polycrystalline graphene sheets are not the cause for degradation in the electrical performance, if the grains were stitched well at the boundary in the growth process.