Filling and Planarizing Deep Trenches with Polymeric Material for Through-Silicon Via Technology

A key driver for 3-D device integration has been through-silicon via (TSV) technology that enables through-chip communication between vertically integrated layers. The TSVs typically have an electrical isolation using a dielectric layer between the silicon and the interconnect metal (e.g., copper). Recently, polymers have been proposed for use as the dielectric isolation layer, and polymers have been shown to increase device reliability by reducing “copper pumping,' where copper pops out from the TSV holes during thermal cycling. Traditionally, spinor spray-coating techniques have been used to fill TSVs with polymer material. However, using those techniques to fill and planarize very deep trenches (∼ 400 μm) and high-aspect-ratio structures has many limitations and usually results in voids, nonplanar surfaces, and lack of polymer flow to the requisite depths. Here, we present a novel process and a tool to completely fill and planarize deep trenches with a polymeric material. We use a combination of a trad...