Technology Breakthrough of Low Temperature, Low Defect, and Low Cost SiGe Selective Epitaxial Growth (L 3 SiGe SEG) Process for 45nm Node and Beyond

We have developed low temperature, low defect and low cost SiGe selective epitaxial growth (L 3 SiGe SEG) process using a high throughput batch type CVD process at first time. Defect is eliminated by low temperature pre-cleaning and recess shape control. As a result, we have achieved the high quality SiGe SEG, improving the compressive channel stress and reducing the junction leakage. We also improved the NMOS short channel effects by low temperature SiGe SEG. Finally, in combination of low temperature SiGe SEG, dual stress SiN liner, and low thermal budget metallization, drive current of 725 muA/mum in PMOS and 940 muA/mum in NMOS were achieved at off current (I off ) =100 nA/mum at drain bias (V DD ) = 1.0 V.