A new CMP-less integration approach for highly scaled totally silicided (TOSI) gate bulk transistors based on the use of selective S/D Si epitaxy and ultra-low gates

In this paper, we present an innovative way of fabricating MOS transistors with totally Ni-silicided (Ni-TOSI) gates without any CMP step before the full gate silicidation process. The combination of the use of a hard-mask-capped ultra-low initial Si gate with a selective S/ D epitaxy step enables us to perform the total gate and junction silicidation in one single step similarly to a standard MOS flow. Full gate silicidation and well-controlled junction silicidation is achieved down to minimum gate lengths of 40 nm. Moreover, we show that the TOSI PMOS device performances are compatible with the 45 nm-node LP requirements. Reliability data is added demonstrating that no additional breakdown mechanisms occur after the TOSI process.