Aerial image ORC checks and their correlation to wafer-edge yield limitation for metals: a study and an OPC resolution

Lithography process variation as well as etch and topography have always been a stubborn challenge for advanced technology nodes, i.e. 14nm and beyond. This variability usually results in defects aggregating around the edge of the wafer and leading to yield loss. A very tight process control is the logical resolution for such issues, nevertheless it might not be possible, or it may slow down the whole design to silicon cycle time. Another degree of difficulty is detecting these defects in ORC and concluding an OPC fix. In this paper, we show that aerial image ORC checks could provide a very useful insight to these defects ahead of time, and that they correlate well with silicon defects highlighted by CFM scan. This early detection upstream enables us to conclude a generic OPC fix for such issues and also improves the total OPC process-window enhancement and eliminates these defects on silicon.