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Haizhou Yin
Haizhou Yin
GlobalFoundries
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Electronic engineering
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Design for manufacturability
4
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Quick Yield Impact Assessment Using Silicon-design Correlation to Address Design Systematics
2021
ASMC | Advanced Semiconductor Manufacturing Conference
Chenlong Miao
Deborah A. Ryan
Haizhou Yin
Monisa Ramesh Babu
Shenghua Song
Eric Chiu
Shobhit Malik
Sriram Madhavan
Michael Wojtowecz
Peter Lin
William Wilkinson
Ct Lim
Panneerselvam Venkatachalam
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Foundry approach for layout risk assessment through comprehensive pattern harvesting and large-scale data analysis
2020
Monisa Ramesh Babu
Shenghua Song
Qian Xie
Pouya Rezaeifakhr
Eric Chiu
Joo Hyun Park
Deborah Ryan
Kiruthika Murali
Praneetha Poluju
Shobhit Malik
Haizhou Yin
Sriram Madhavan
Panneerselvam Venkatachalam
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Rapid yield ramp using closed loop DFM and overlay process window qualification flow
2018
ASMC | Advanced Semiconductor Manufacturing Conference
Michael Wojtowecz
Deborah Ryan
Karthik Krishnamoorthy
Nabil Azad
Haizhou Yin
Pietro Babighian
Uwe Paul Schroeder
Mark Duggan
Panneerselvam Venkatachalam
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Aerial image ORC checks and their correlation to wafer-edge yield limitation for metals: a study and an OPC resolution
2017
Tamer Desouky
Yixiao Zhang
Mark Terry
Haizhou Yin
Muhammed Pallachali
Nicolai Petrov
Teck Jung Tang
Fadi Batarseh
Ahmed Khalil
Pietro Babighian
Rohan Deshpande
Deborah Ryan
Rao Desineni
Shweta Shokale
Feng Wang
Sang-Kee Eah
Jiechang Hou
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