Power-aware and cost-efficient state encoding in non-volatile memory based FPGAs

Non-volatile memory (NVM)-based FPGAs are expected to replace traditional SRAM-based FPGAs to achieve higher scalability, lower leakage power, and better reliability. In NVM-based FPGAs, dynamic power is the dominant power factor, and flip-flops exhibit the most intensive switching activities. While flip-flops can be implemented with NVM elements such as Magnetic Tunnel Junctions (MTJ), NVM cells suffer from high write energy, making it necessary to reduce dynamic power by minimizing bit flips. Furthermore, flip-flops are used to implement finite state machines, whose power and hardware cost are largely determined by state encoding. In this work, a new state encoding algorithm is proposed to reduce bit flips during state transitions within limited number of flip-flops. The proposed scheme, consisting of a transition graph model, an encoding graph conflict removing algorithm and a hardware efficient encoding algorithm, is able to reduce flip-flops used by 85% and reduce state transition bit flips by 41.1% compared with existing popular encoding solutions.