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H. Abiko
H. Abiko
NEC
Electronic engineering
CMOS
Salicide
Ion implantation
Sheet resistance
5
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74
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A high-performance 0.18-/spl mu/m merged DRAM/Logic technology featuring 0.45-/spl mu/m/sup 2/ stacked capacitor cell
1999
IEDM | International Electron Devices Meeting
M. Hamada
K. Inoue
R. Kubota
M. Takeuchi
Masato Sakao
H. Abiko
H. Kawamoto
Hiromu Yamaguchi
H. Kitamura
S. Onishi
K. Koyanagi
K. Mikagi
Koji Urabe
Tetsuya Taguwa
T. Yamamoto
N. Nagai
I. Shirakawa
S Kishi
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A voltage-regulated static keeper technique for high-performance ASICs
1998
ASICON | International Conference on ASIC
H. Kanno
T. Saeki
H. Abiko
A. Kubo
K. Tokashiki
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A 6 Gbps CMOS phase detecting DEMUX module using half-frequency clock
1998
VLSIC | Symposium on VLSI Circuits
Kazuyuki Nakamura
Muneo Fukaishi
H. Abiko
A. Matsumoto
Michio Yotsuyanagi
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A new cobalt salicide technology for 0.15 /spl mu/m CMOS using high-temperature sputtering and in-situ vacuum annealing
1995
IEDM | International Electron Devices Meeting
K. Inoue
K. Mikagi
H. Abiko
Takamaro Kikkawa
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Citations (12)
A new salicide process (PASET) for sub-half micron CMOS
1992
VLSIT | Symposium on VLSI Technology
I. Sakai
H. Abiko
H. Kawaguchi
T. Hirayama
L.E.G. Johansson
K. Okabe
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Citations (27)
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