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K. Cox
K. Cox
Motorola
Electronic engineering
CMOS
Static random-access memory
Interconnection
Electrical engineering
5
Papers
8
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A partially depleted 1.8 V SOI CMOS SRAM technology featuring a 3.77 /spl mu/m/sup 2/ cell
2000
VLSIT | Symposium on VLSI Technology
K. Cox
John D. Scott
S. Bishop
Mousumi Bhat
B. Nettleton
D. Pan
Mark G. Hamilton
David Chang
L. Day
P. Schani
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17.4 A Partially Depleted 1.8V SO1 CMOS SRAM Technology Featuring a 3.77pm2 Cell
2000
K. Cox
John D. Scott
D. Pan
Mark G. Hamilton
U. Chang
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A highly versatile 0.18 /spl mu/m CMOS technology with dense embedded SRAM
2000
VLSIT | Symposium on VLSI Technology
Mousumi Bhat
S. Shi
P. Grudowski
C Feng
B. Lee
R. Nagabushnam
J. Moench
C. Gunderson
P. Schani
L. Day
S. Bishop
H. Tian
J. Chung
Craig S. Lage
J. Ellis
N. Herr
Percy V. Gilbert
A. Das
F Nkansah
M. Woo
Mark L. Wilson
D. Derr
L. Terpolilli
K. Weidemann
R. Stout
A. Hamilton
T. Lii
F. Huang
K. Cox
John D. Scott
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The effect of HF processing on gate oxide degradation in aggressive poly buffered LOCOS isolation
1996
IEEE Electron Device Letters
K. Cox
M. Chonko
C. Honcik
S. VanDyke
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Performance of a sequentially deposited Ti/TiN/AlCuSi metallization structure
1991
VLSI-MIC | International IEEE VLSI Multilevel Interconnection Conference
S. Gonzales
C. Magnella
B. Boeck
K. Cox
L. Huebinger
R. Mosely
J. Nulman
H. Gilboa
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