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P. Schani
P. Schani
Electronic engineering
Electrical engineering
Engineering
CMOS
Static random-access memory
2
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2
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0
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2024
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A partially depleted 1.8 V SOI CMOS SRAM technology featuring a 3.77 /spl mu/m/sup 2/ cell
2000
VLSIT | Symposium on VLSI Technology
K. Cox
John D. Scott
S. Bishop
Mousumi Bhat
B. Nettleton
D. Pan
Mark G. Hamilton
David Chang
L. Day
P. Schani
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A highly versatile 0.18 /spl mu/m CMOS technology with dense embedded SRAM
2000
VLSIT | Symposium on VLSI Technology
Mousumi Bhat
S. Shi
P. Grudowski
C Feng
B. Lee
R. Nagabushnam
J. Moench
C. Gunderson
P. Schani
L. Day
S. Bishop
H. Tian
J. Chung
Craig S. Lage
J. Ellis
N. Herr
Percy V. Gilbert
A. Das
F Nkansah
M. Woo
Mark L. Wilson
D. Derr
L. Terpolilli
K. Weidemann
R. Stout
A. Hamilton
T. Lii
F. Huang
K. Cox
John D. Scott
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Citations (2)
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