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Saranyu Chattopadhyay
Saranyu Chattopadhyay
Indian Institute of Technology Kharagpur
Computer science
Condensed matter physics
Engineering
Electronic engineering
Electrical impedance
5
Papers
9
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Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition.
2021
arXiv: Logic in Computer Science
Saranyu Chattopadhyay
Florian Lonsing
Luca Piccolboni
Deepraj Soni
Peng Wei
Xiaofan Zhang
Yuan Zhou
Luca P. Carloni
Deming Chen
Jason Cong
Ramesh Karri
Zhiru Zhang
Caroline Trippel
Clark Barrett
Subhasish Mitra
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LeGO: A Learning-Guided Obfuscation Framework for Hardware IP Protection
2021
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Abdulrahman Alaql
Saranyu Chattopadhyay
Prabuddha Chakraborty
Tamzidul Hoque
Swarup Bhunia
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Citations (5)
A-QED Verification of Hardware Accelerators
2020
DAC | Design Automation Conference
Eshan Singh
Florian Lonsing
Saranyu Chattopadhyay
Maxwell Strange
Peng Wei
Xiaofan Zhang
Yuan Zhou
Deming Chen
Jason Cong
Priyanka Raina
Zhiru Zhang
Clark Barrett
Subhasish Mitra
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Citations (3)
Machine Learning Assisted Accurate Estimation of Usage Duration and Manufacturer for Recycled and Counterfeit Flash Memory Detection
2019
ATS | Asian Test Symposium
Saranyu Chattopadhyay
Preeti Kumari
Biswajit Ray
Rajat Subhra Chakraborty
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A novel technique for implementing reactance in spin domain using Spin Hall Effect
2018
Microelectronics Journal
Saranyu Chattopadhyay
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