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Jae-Chul Kim
Jae-Chul Kim
Samsung
Materials science
Electronic engineering
Wafer
Transistor
Dielectric
4
Papers
14
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Performance-Power Management Aware State-of – the-Art 5nm FinFET Design(5LPE) with Dual CPP from Mobile to HPC Application
2020
IEDM | International Electron Devices Meeting
Jae-Hun Jeong
Young-Gun Ko
Kihwang Son
Sung-Won Kim
Ju-youn Kim
Jeongmin Choi
Hyung-Jong Lee
Ho Lee
Sihyung Lee
Chunghwan Shin
Heebum Hong
Sung-il Jo
Young-Ho Lee
Byungha Choi
Jae-Chul Kim
Minseong Lee
Kyunghoon Jung
Yuri Yasuda-Masuoka
Jong-Mil Youn
Gitae Jeong
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Local Variation-Aware Transistor Design through Comprehensive Analysis of Various Vdd/Temperatures Using Sub- 7nm Advanced FinFET Technology
2020
VLSIT | Symposium on VLSI Technology
Soyoun Kim
Seung-Kwon Kim
Taiko Yamaguchi
Jae-Chul Kim
Byung-Gook Park
Masuoka Yuri
Sang-Deok Kwon
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Impact of TSV proximity on 45nm CMOS devices in wafer level
2011
IITC | International Interconnect Technology Conference
Sung-Dong Cho
Sin-Woo Kang
Kang-Wook Park
Jae-Chul Kim
Ki-Young Yun
Kisoon Bae
Woon-Seob Lee
Sangwook Ji
Eun-ji Kim
Jang-ho Kim
Yeong L. Park
Eun Seung Jung
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Citations (13)
Highly manufacturable Cu/low-k dual damascene process integration for 65nm technology node
2004
IITC | International Interconnect Technology Conference
K.-W. Lee
Hyun Jin Shin
J.W. Hwang
Seo-Woo Nam
Young-Joon Moon
Young Jin Wee
I.G. Kim
W.J. Park
Jae-Chul Kim
Seungmoo Lee
Kwang Myeon Park
H.K. Kang
Kwang Pyuk Suh
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