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Takayoshi Minami
Takayoshi Minami
Fujitsu
Engineering
Electronic engineering
Lithography
Logic gate
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4
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1
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Poly-width-modification method for canceling layout-dependent characteristic variations for low-standby-power CMOS technologies
2009
ASMC | Advanced Semiconductor Manufacturing Conference
Satoshi Nakai
Kazushi Fujita
Takayoshi Minami
Junichi Mitani
Toshio Sawano
Tatsuo Chijimatsu
Tatsuya Deguchi
Satoru Asai
Masato Suga
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Design-friendly DFM rule
2006
Morimi Osawa
Takayoshi Minami
Hiroki Futatsuya
Satoru Asai
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Optimization of contact hole lithography for 65-nm node Logic LSI
2006
Yuji Setta
Hiroki Futatsuya
Atsushi Sagisaka
Tatsuo Chijimatsu
Takayoshi Minami
Fumitoshi Sugimoto
Seiichi Ishikawa
Satoru Asai
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Local flare effects and correction in ArF lithography
2003
VLSIT | Symposium on VLSI Technology
Teruyoshi Yao
Morimi Osawa
Takayoshi Minami
N. Yamamoto
Hajime Aoyama
G. Okuda
Toshio Sawano
I. Kamatsuki
F. Sugimoto
Hiroki Futatsuya
Kaoru Kobayashi
Kozo Ogino
Hiromi Hoshino
Yasuhide Machida
Hiroshi Arimoto
Satoru Kawasaki Asai
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