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C. O'Brien
C. O'Brien
Texas Instruments
NMOS logic
Electronic engineering
Static random-access memory
PMOS logic
Thermal stability
2
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37
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A designer friendly 45nm high performance technology with in-situ C-doped e-SiGe & dual stress liner in SRAM
2008
VLSIT | Symposium on VLSI Technology
Rajesh Khamankar
C. Bowen
H. Bu
D. Corum
I. Fujii
Yiming Gu
B. Hornung
T.S. Kim
Brian K. Kirkpatrick
K. Kirmse
Anand T. Krishnan
C. Lin
L. Liu
T. Lowry
C. Montgomery
Oluwamuyiwa Oluwagbemiga Olubuyide
Steven L. Prins
Deborah J. Riley
Shaofeng Yu
James Walter Blatchford
C. Machala
C. O'Brien
Gregory B. Shinn
T. Grider
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SRAM Cell Static Noise Margin and VMIN Sensitivity to Transistor Degradation
2006
IEDM | International Electron Devices Meeting
Anand T. Krishnan
Vijay Reddy
D. Aldrich
Jayesh C. Raval
Kim Hardam Christensen
J. Rosal
C. O'Brien
Rajesh Khamankar
Andrew Marshall
W. K. Loh
Randy Mckee
Srikanth Krishnan
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Citations (37)
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