Advanced flip-chip package production solution for 40nm/28nm technology nodes

The key technology challenges and solutions in the packaging and assembly of large dies and/or fine pitch on organic substrates for both the 40 and 28 nm technology nodes are reported. Both eutectic PbSn, Pb-free solders, and Cu pillar bumps were used in the flip chip packages. The key challenge of chip-package-integrations (CPI) due to the use of fragile extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL) layer has been resolved by the redesigning of the BEOL structure and optimizing the materials set including both the organic substrate and solder materials, along with process improvements.